AMD Achieves First TSMC N2 Product Silicon Milestone
AMD announced that its next-generation EPYC processor, codenamed “Venice,” is the first HPC product in the industry to be taped out and brought up on the TSMC advanced 2nm (N2) process technology.
At this year’s Hot Chips event, Intel provided the first in-depth look at its next-generation Xeon product lineup. It is built on a new platform architecture.
The platform marks an important evolution for Xeon by introducing processors with a new Efficient-core (E-core) architecture alongside its well-established Performance-core (P-core) architecture. Code-named Sierra Forest and Granite Rapids, respectively, these new products will bring simplicity and flexibility to customers, offering a compatible hardware architecture and shared software stack to tackle critical workloads such as artificial intelligence.
“It is an exciting time for Intel and its Xeon roadmap. We recently shipped our millionth 4th Gen Xeon, our 5th Gen Xeon (code-named Emerald Rapids) will launch in the fourth quarter of 2023 and our 2024 portfolio of data center products will prove to be a force in the industry,” said Lisa Spelman, Intel corporate vice president and general manager of Xeon Products and Solutions.
The new Xeon platform utilizes modular system-on-chips for increased scalability and flexibility to deliver a range of products that meet the growing scale, processing, and power efficiency needs for AI, cloud, and enterprise installations. The new architecture also helps customers maximize their investment by offering two different socket-compatible processors. Xeon processors with E-cores are enhanced to deliver density-optimized computing in the most power-efficient manner. Processors with P-cores are optimized to deliver the lowest total cost of ownership for high-core performance-sensitive workloads and general-purpose compute workloads.