IBM and Siemens Collaborate to Advance Nanostack Architecture

IBM, in collaboration with Siemens, has announced new research intended to advance nanostack architecture, a novel transistor framework introduced earlier this year. The partnership integrates IBM's leadership in semiconductor device innovation with Siemens' proficiency in electronic design automation (EDA), process simulation, lithography optimization, and advanced manufacturing software to accelerate the development of nanostack.

Nanostack represents the industry’s first known three-dimensional, nanosheet-based design, which vertically stacks and staggers transistors to achieve higher density—packing nearly 100 billion transistors into a space the size of a fingernail at its current 7-angstrom node. The design also permits the use of different material combinations within each stacked layer to optimize performance and power efficiency for each transistor independently. These innovations facilitate significant advancements in energy efficiency, performance, and SRAM scaling.

Earlier this year, IBM demonstrated the functional viability of the nanostack architecture. Current efforts are focused on the additional advancements required to prepare the technology for large-scale manufacturing. Through this collaboration, IBM and Siemens will work to refine the design, simulation, and lithography techniques necessary for this and future nanostack generations beyond the 7-angstrom node. This includes the development of advanced virtual models to optimize designs and address fabrication challenges before physical production.

"Nanostack is a scalable transistor platform designed to shift device scaling from 2D to 3D, representing a new paradigm for the semiconductor industry and a path forward for the logic scaling needed to support AI and other emerging technologies over the coming decade,” stated Huiming Bu, Vice President of Silicon Technology R&D at IBM. “We are thrilled to work with Siemens as we continue to advance this technology and explore new approaches to extend angstrom-level scaling with nanostack.”

“Scaling semiconductors into the angstrom era demands tightly coupled co-optimization between device physics, EDA design, and manufacturing software. As physical AI places extraordinary demands on silicon architecture, IBM’s 3D nanostack design represents a pivotal leap forward,” noted Ankur Gupta, Executive Vice President, EDA IC Portfolio at Siemens. “Siemens’ collaboration with IBM to advance virtual modeling, simulation, lithography, and design software optimizations needed to address physical limitations early and accelerate the development of these complex architectures is truly pioneering.”